X
X
R
R
P
P
7
7
7
7
1
1
4
4
 
 
Q
Q
u
u
a
a
d
d
 
 
C
C
h
h
a
a
n
n
n
n
e
e
l
l
 
 
D
D
i
i
g
g
i
i
t
t
a
a
l
l
 
 
P
P
W
W
M
M
 
 
S
S
t
t
e
e
p
p
 
 
D
D
o
o
w
w
n
n
 
 
C
C
o
o
n
n
t
t
r
r
o
o
l
l
l
l
e
e
r
r
 
 
 
?2011 Exar Corporation
4/29
Rev. 1.1.6
Digital Input/Output Pins (GPIO0-GPIO5) and ENABLE
3.3V CMOS logic compatible, 5V tolerant.
Parameter
Min.
Typ.
Max.
Units
 
Conditions
Enable Pin Threshold
1.
1.14
1.2
V
    Chip Enable rising threshold
Input Pin Low Level
 
 
0.8
V
"
 
Input Pin High Level
2.0
 
 
V
"
 
Input Pin Leakage Current
 
 
10
"
V
IO
=3.3V
Input pin Capacitance
5
 
pF
    
Output Pin Low Level
 
 
0.4
V
"   I
SINK
=1mA
Output Pin High Level
2.4
 
 
V
"
I
SOURCE
=1mA
Output Pin High Level (no load)
 
3.3
3.6
V
"
I
SOURCE
=0mA
I
2
C Specification
Parameter
Min.
Typ.
Max.
Units
 
Conditions
I
2
C Speed
 
 
400
kHz
    Based upon I
2
C master clock
Input Pin Low Level, V
IL
 
 
1.0
V
    
Input Pin High Level, V
IH
 
2.31
 
 
V
    
Hysteresis of Schmitt Trigger
Inputs, V
HYS
 
0.165
 
 
V
 
 
Output Pin Low Level (open
drain or collector) V
OL
 
 
 
0.4
V
    I
SINK
=3mA
Input Leakage Current
-10
 
10
 
Input is between 0.33V and 2.31V
Output Fall Time from V
IHMIN
 to
VILMAX
20+0.1C
b
3
 
 
250
ns
 
With a bus capacitance from 10pF to
400pF
Capacitance for each I/O Pin
 
 
10
pF
 
 
Note 3: C
b
 is the capacitance of one bus in pF
Gate Drivers
Parameter
Min.
Typ.
Max.
Units
 
Conditions
GH, GL Rise and Fall Time
 
30
 
ns
 
At 10% to 90% of full scale pulse.
1nF C
load
 
GH, GL Pull-up On-State Output
Resistance
 
6
 
&
    
GH, GL Pull-down On-State
Output Resistance
 
3
 
&
    
GH, GL Pull-down Off-State
Output Resistance
 
50
 
k&
    VIN=VCCD=0V
 
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